As semiconductor designers continually look to increase the functionality of integrated chips, the size of logic components on the integrated chip is continually being pushed into the realm of smaller technology nodes to fit the functionality into smaller areas. Conventionally, only two-dimensional (2D) planes were used to integrate more functionality into a smaller area through the use of conventional complementary metal oxide semiconductor (CMOS) scaling, multiple IP cores in a single die (System-on-Chip, SoC), multiple dies in a single package (Multi-Chip Package, MCP), and multiple integrated circuits (ICs) on a printed Circuit Board (PCB).
More recently, the third-dimension (e.g., the vertical dimension) has started to become exploited to integrate even more functionality into a smaller area through the use of System-in-Package (SiP) technology, in which multiple dies or chips are vertically stacked in a single IC package (e.g., a chip on chip configuration), and interconnected by means of wire-bonds to the substrate, and Package-on-Package (PoP) technology, in which multiple packaged chips are vertically stacked. The 3D stacking of chips not only offers a smaller physical package but also shortens wires, which can allow for higher performance.
As with conventional 2D integrated chips, these new 3D integrated chips could benefit from a reduction in parametric yield loss. Specifically, process variation across integrated chips is recognized as a major source of parametric yield loss, which occurs because a fraction of manufactured integrated chips (conventional 2D integrated chips or newer 3D integrated chips) do not satisfy timing or power constraints of the customer. On the other hand, both integrated chip performance and integrated chip leakage power depend on supply voltage. This dependence can be used for converting the fraction of too slow or too leaky integrated chips into acceptable integrated chips by adjusting their supply voltage. This technique is called selective voltage binning (SVB).
SVB is used widely in the semiconductor industry for minimizing power consumption of integrated chips while optimizing supply voltage across a predetermined process space. SVB depends upon the integrated chips being divided into groups (bins) and each group is assigned its individual process space. During manufacture of the integrated chips, the individual process space is burned into the integrated chip using an electronic chip identifier (ECID) such that each integrated chip knows the process space under which it falls. Therefore, for example, if the integrated chip knows it falls under a slow process space, the integrated chip can set its supply voltage high using a voltage regulator, or alternatively, if the integrated chip knows it falls under a fast process space, the integrated chip can set its supply voltage low using the voltage regulator. In any event, the purpose of the SVB is for the integrated chip to be configured to set its supply voltage to minimize leakage based on its assigned process space.
However, with a 3D integrated chip stack, there is the possibility for multiple ECIDs and multiple voltage rails for each chip in the 3D integrated chip stack. Therefore, a problem arises as to how a 3D integrated chip stack should be configured to set the one or more supply voltages when there are multiple different speeds across multiple process spaces.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.